Advanced VLSI-class semiconductor devices are being designed with sub-micron moat-to-moat spacing. Working (or active) semiconductor devices are fabricated on the moat region on the semiconductor wafer. These devices must be adequately isolated from one another to prevent adverse interaction (e.g., leakage current or shorting) between these devices. A well known technique for forming isolation regions between the moat regions is the LOCOS field oxidation technique, which has become an industry mainstay. Conventional LOCOS techniques, however, have been inadequate or marginal at best when used with sub-micron VLSI products. In particular, "moat encroachment" (also known as "bird's beaking") is a major problem. It is caused be lateral oxidation into the moat regions during field oxide growth. This encroachment at moat edges and comers results in a drastic decrease of moat dimensions and is severely detrimental for maintaining sub-micron moat-to-moat geometries.
Several isolation techniques have been developed in recent years for use with VLSI CMOS and BiCMOS products. For instance, the Poly-Buffered LOCOS (PBL) Isolation technique is currently used with VLSI designs having 1.2 micron minimum moat-to-moat spacing. Poly-buffered LOCOS is a modification to the industry standard LOCOS isolation process. The modification includes the step of adding a thin buffer layer of polysilicon (poly) between the underlying pad oxide and the overlying moat nitride film. The polysilicon layer allows the use of a thick moat nitride film during the field oxidation process by relieving stresses in the silicon lattice normally present during LOCOS oxidation.